Application of the hottest CPLD in short-range rec

2022-08-09
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The application of CPLD in short-range reconnaissance radar

the development of radar technology largely depends on the development of components, especially integrated circuits (ICS). With the development of large-scale and very large-scale integrated circuits, the volume of radar is becoming smaller and smaller, the weight is becoming lighter and lighter, and the function is becoming more and more complex. Today, with the development of integrated circuits, the IC with fixed functions can no longer meet the increasing design needs of people, so the construction of universal chip programmable logic devices for various purposes came into being. PLD greatly simplifies the system design, reduces the scale of the system, improves the reliability of the system, and can meet various application needs, especially for small batch and multi variety military products development. This paper introduces the development, current situation, main types, characteristics and selection criteria of PLD devices, and introduces the application of complex programmable logic device (CPLD) in vehicle/portable short-range battlefield reconnaissance radar

2 development and current situation of programmable logic devices [1], [2]

PLD is actually an and or two-level structure device, whose final logic structure and function are determined by user programming, and has the advantages of both standard logic devices and semi custom logic devices. Early PLD devices include pal (programmable array logic), PLA (the storage length of glass fiber is increased by about 1 times after EMI (2) 00) and gal (generalarray logic). These PLD devices are relatively simple. Due to the limitations of process conditions, they can only realize small-scale circuits, generally only a few hundred gates

after the 1980s, EPLD (erasable programmable logic device), CPLD (when complex programmd1 <5, the size deviation and appearance quality are qualified; able logic device) and FPGA (field programmable gate array), which are extended on the basis of PAL structure, have emerged. They all have the characteristics of flexible architecture and logic unit programming, high integration and wide application range. These devices are not only large-scale, highly integrated, but also more flexible to use

since the 1990s, PLD devices have developed rapidly and are moving towards high integration, high speed and low price. They mainly have the following characteristics:

(1) the integration is getting higher and higher. For example, the 10K series of Altera company has more than 250000 gates, with more than 10000 registers and 40kbit embedded memory, making it possible to integrate complex signal processing algorithms. Raphael series has more than 1million doors, which integrates all the advantages of FLE x10k, FLEX6000 and MAX7000, and can be used for single-chip system design

(2) in system programming (ISP) and road reconfiguration (ICR) technology make PLD have the advantages of short development cycle and easy change of design scheme

(3) embedded memory technology embeds a certain amount of memory in PLD. The memory types include dual port SRAM, ROM, FIFO, etc., which can be used to store the coefficients and intermediate results of signal processing

(4) the clock locking and frequency doubling technology is adopted to solve the problem of clock pulse delay and skew, and make the internal clock of PLD higher. The speed of a single 16bit multiplier can reach more than 100MHz, which is what is needed for high-speed real-time signal processing with large bandwidth

(5) electronic design automation (EDA) tools are increasingly enriched and improved, which facilitates users' input, synthesis and Simulation of design

pld has many advantages above, so its application field is expanding, and its application in the field of radar signal processing is also increasingly active

3 types and selection of programmable logic devices (PLD) [2]

there are many kinds of PLD devices. According to the basic structure, it can be divided into two categories: one is CPLD extended on the basis of PAL structure, and the other is FPGA devices of standard gate array logic unit type. The internal wiring of CPLD is relatively fixed, and the delay parameters of the logic to be realized can be determined in advance. The internal delay is small, which is conducive to the device working at a higher frequency and has a higher logic utilization. It is especially suitable for the implementation of counters, arithmetic operations, control circuits and more complex state machines. The core of FPGA circuit is the configurable logic block. Users can program the logic block and the interconnection resources between the logic blocks, so as to realize complex logic functions. Compared with CPLD, FPGA has higher integration and can realize more complex circuit functions, but its speed is low and its predictability is poor. Whether the timing meets the requirements can be determined only after the internal layout and wiring of the chip are completed

on the other hand, PLD devices can also be divided into primary programming type using anti fuse technology and reprogrammable type using SRAM, flash RAM, EPROM or EEPROM according to the number of programmable times. The former has the characteristics of small volume, high integration, low interconnect characteristic impedance, high speed, etc., and does not need external PROM and EPROM, and its disadvantages are also obvious: it can only be programmed once. The reprogrammable FPGA using SRAM stores the functions of each logic block and their interconnection mode in the SRAM storage unit in the chip. Its biggest advantage is that it can be reprogrammed quickly and has the ability of reconfigurable system, which is especially suitable for product prototype design. The disadvantage is the need for external prom or EPROM. CPLD using flashram, EPROM or EEPROM can be reprogrammed without external PR, including hydraulic universal testing machine and electronic universal testing machine om or EPROM, but the cost is higher than that of one-time programmer, and usually the system cannot be reconstructed

as for the selection of PLD, first of all, users can determine which type of PLD device to choose according to the design needs. Considering the circuit functions that need to be realized, if it is a planned synchronous design, such as state converter, address decoder and large-scale binary synchronous counter, CPLD should be selected; If it is multi-level logic application, fast pipeline design or large register circuit, FPGA is more appropriate. Considering the application occasions, if it is used in aerospace and military fields, the one-time programmable PLD of anti fuse technology is the first choice. If it is the prototype design of the product, the programmable PLD device should be selected

secondly, select the products of a certain manufacturer. There are many manufacturers producing similar devices. Users must comprehensively consider software support, margin of product design performance improvement, continuity and scalability of design and application, cost performance and other factors to select the products of appropriate device manufacturers

finally, select a specific model from the products of a selected manufacturer according to the chip capacity, packaging form, speed level, temperature range, etc

selecting a suitable PLD chip is the first step to a successful design. If the design is required to be completed in a short time, an appropriate margin can be left when selecting a chip; If time permits, the model of the chip can be determined after the simulation is completed

the application of 4cpld in radar multi-function signal generator

the multi-function signal generator of short-range battlefield reconnaissance radar needs to generate the following signals under the control of the radar general controller: pseudo code phase modulation excitation signal, reference code signal of multiple distance branches, long-range and short-range sinusoidal frequency modulation signal, self-test result, etc. The generation of digital signal can be realized by PLD. Since this is a regular synchronous design problem, we choose CPLD type devices. Considering the factors of capacity, speed, power consumption, design tools and so on, we choose ATMEL's atv2500l-30pi to realize. Its functional block diagram is shown in Figure 1

driven by the clock, the pseudo-random code generator generates a pseudo-random code signal of a specific length as a code. The code is excited to form a pseudo-random code phase modulation excitation signal. At the same time, the pseudo-random code generates the reference code of the search distance branch and the reference code of the listening distance branch with different delays under the control of the delay control signal. After dividing the clock, it also generates a square wave signal, The period of square wave signal can be controlled by long-range and short-range control signal. It can be used as sinusoidal frequency modulation signal after filtering and amplification. The self-test circuit performs self-test on various digital signals generated, and forms stable and reliable self-test results. After using CPLD devices, all the above functions are realized, and the power consumption is only 20MW

The application of

5cpld in radar signal processor

the signal processor of short-range battlefield reconnaissance radar needs to sample the output signals of multiple distance branches at the same time, a/D transformation, data storage and real-time digital signal processing. The sampling control signal, a/D conversion channel selection signal, data storage address signal and storage control signal can also be generated by PLD. Since this is a problem of large-scale synchronous counting, we also choose ATMEL's atv2500l-30pi to realize it by comprehensively considering various factors. Its functional block diagram is shown in Figure 2

driven by the clock, the signal with a certain duty cycle is obtained by the frequency divider as the sampling control signal to control the startup of the A/D conversion circuit, and the selection of the A/D conversion channel is controlled by the channel selection signal generated by the channel selection counter. After a/D conversion, the analog signal is converted into digital signal, which is stored in dual port RAM under the control of storage control signal, and the address signal of data storage is automatically generated by the data storage address generator. In this way, only an A/D converter, a dual port RAM and a sampling control circuit realized by CPLD are needed in the signal processor, and the analog signals output by each distance branch are orderly converted into digital signals and automatically stored in the designated area of dual port RAM according to certain requirements. After using CPLD, it only needs 10MW to realize all the functions of the sampling control circuit

6 conclusion

this paper uses CPLD to complete the design of radar signal generation circuit and sampling control circuit that used to need circuit board. The designed CPLD has been applied in a short-range battlefield reconnaissance radar. The practice shows that the application of CPLD simplifies the system structure, reduces the volume, reduces the power consumption, and improves the reliability of the system

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